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NCP361, NCV361
Operation
NCP361 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V out pin, against positive
overvoltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
V out
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built ? in undervoltage lock out (UVLO)
circuit. During V in positive going slope, the output remains
disconnected from input until V in voltage is above 3.0 V
nominal. The FLAGV output is pulled to low as long as V in
does not reach UVLO threshold. This circuit has a 70 mV
I load
I lim
Overload
Retrieve
normal
operation
hysteresis to provide noise immunity to transient condition.
V in (V)
20 V
OVLO
UVLO
0
V out
OVLO
UVLO
t on
Figure 21. Overcurrent Event Example
FLAG Output
NCP361 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon as: 1.2 V < V in < UVLO,
V in > OVLO, I charge > I limit , T J > 150 ° C. When NCP361
recovers normal condition, FLAG is held high. The pin is
an open drain output, thus a pull up resistor (typically 1 M W
? Minimum 10 k W ) must be provided to V CC . FLAG pin is
an open drain output.
0
Figure 20. Output Characteristic vs. V in
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
Overvoltage Lockout (OVLO)
To protect connected systems on V out pin from
overvoltage, the device has a built ? in overvoltage lock out
(OVLO) circuit. During overvoltage condition (OVLO
exceeds), the output remains disabled and FLAG is tied
low, as long as the input voltage is higher than OVLO ?
hysteresis. This circuit has a 100 mV hysteresis to provide
noise immunity to transient conditions .
Overcurrent Protection (OCP)
The NCP361 integrates overcurrent protection to
prevent system/battery overload or defect. The current
limit threshold is internally set at 750 mA. This value can
be changed from 150 mA to 750 mA by a metal tweak,
please contact your ON Semiconductor representative for
availability. During current fault, the internal PMOS FET
is automatically turned off (5 m s) if the charge current
exceeds I lim . NCP361 goes into turn on and turn off mode
as long as defect is present. The internal ton delay (4 ms
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
The NCP361 includes an internal PMOS FET to protect
the systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
R DS(on) , during normal operation, will create low losses on
V out pin, characterized by V in versus V out dropout.
ESD Tests
The NCP361 fully supports the IEC61000 ? 4 ? 2, level 4
(Input pin, 1 m F mounted on board). That means, in Air
condition, V in has a ± 15 kV ESD protected input. In
Contact condition, V in has ± 8 kV ESD protected input.
Please refer to Figure 22 to see the IEC61000 ? 4 ? 2
electrostatic discharge waveform.
typical) allows limiting thermal dissipation. The Flag pin
goes to low level when an overcurrent fault appears. That
allows the microcontroller to count defect events and turns
off the PMOS with EN pin.
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